On-chip debug (OCD) interfaces can provide chip-level control of a target device and are a primary vector used by engineers, researchers, and hackers to extract program code or data, modify memory contents, or affect device operation on the fly. Depending on the complexity of the target device, manually locating available OCD connections can be a difficult and time-consuming task, sometimes requiring physical destruction or modification of the device.

Designed by Grand Idea Studio, JTAGulator is an open-source hardware tool that assists in identifying OCD connections from test points, vias, or component pads on a target device. It also could be used as a simple logic analyzer or as a development system for the Parallax Propeller microcontroller that is on the board.

The JTAGulator is powered from the host computer's USB port and uses an industry-standard FTDI FT232RL device to provide the USB connectivity. The device will appear as a Virtual COM port and will have a COM port number automatically assigned to it. All communication is 115200 bps, 8 data bits, no parity, 1 stop bit. Use a terminal program (e.g. HyperTerminal, PuTTY, CoolTerm, picocom, or screen) to communicate with the JTAGulator.

Attach the target's points to the JTAGulator using the screw-in terminal blocks or via the 2×5 male headers, starting at CH0 and incrementing sequentially as needed. Ensure there is a shared GND connection between the JTAGulator and target board. VADJ should not be connected to the target board (it is made available on the headers for testing and future use).

On-Chip Debug Interface Board Features

• 24 I/O channels with input protection circuitry
• Adjustable target voltage: 1.2V to 3.3V
• Supported target interfaces (as of firmware v1.1): JTAG/IEEE 1149.1, UART/asynchronous serial
• USB interface for direct connection to host computer (PC, Macintosh, or *nix)

Note: Proper use of this tool requires basic electronics knowledge. To avoid damage to the JTAGulator or target circuitry, please take care to ensure the proper target voltage level is set. Some on-chip debug interfaces may not be detectable if password protection or other security mechanisms are implemented.

On-Chip Debug Interface Board Resources

• JTAGulator User Guide
• Virtual COM Port Drivers for Windows, Mac and Linux
• JTAGulator Schematic
• JTAGulator Block Diagram
• JTAGulator Gerber Files
• JTAGulator Source Code Repository
• Video: JTAGulator Introduction
• Video: UART Discovery with JTAGulator
• Video: Assisted Discovery of On-Chip Debug Interfaces using JTAGulator
• Slides from detailed presentation about JTAGulator