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Design Recipes for FPGAs US$52.95

Design Recipes for FPGAs

This book provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, the book includes easy-to-find design techniques and templates at all levels, together with functional code, which you can easily match and apply to their application.

The easy-to-find structure begins with a design application to demonstrate the key building blocks of FPGA design and how to connect them, enabling experienced FPGA designers to quickly select the right designs for their applications, while providing the less experienced a road map to solving their specific design problems.

Written in an informal and easy-to-grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to actually demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create real-world designs that fit the device required and which are fast and reliable to implement. An accompanying CD-ROM contains code, test benches and simulation command files for ModelSim.

This book will be an indispensable, well-thumbed resource for FPGA designers of all levels of experience.

Book Details

  • Paperback: 320 pages
  • Publisher: Newnes; Pap/Cdr edition (June 18, 2007)
  • Language: English
  • Dimensions: 9.5 x 7.4 x 0.8 inches
  • Shipping Weight: 6.8 pounds

Table of Contents

    Section 1: Introduction

      Chapter 1: Introduction
        1.1 Overview
        1.2 Why FPGAs?
      Chapter 2: An FPGA Primer
        2.1 Introduction
        2.2 FPGA Evolution
        2.3 Programmable Logic Devices
        2.4 Field Programmable Gate Arrays
        2.5 FPGA Design Techniques
        2.6 Design Constraints Using FPGAs
        2.7 Summary
      Chapter 3: A VHDL Primer – The Essentials
        3.1 Introduction
        3.2 Entity – Model Interface
        3.3 Architecture – Model Behavior
        3.4 Process – Basic Functional Unit in VHDL
        3.5 Basic Variable Types and Operators
        3.6 Decisions and Loops
        3.7 Hierarchical Design
        3.8 Debugging Models
        3.9 Basic Data Types
        3.10 Summary
      Chapter 4: Design Automation and Testing for FPGAs
        4.1 Simulation
        4.2 Libraries
        4.3 Synthesis
        4.4 Physical Design Flow
        4.5 Place and Route
        4.6 Timing Analysis
        4.7 Design Pitfalls
        4.8 VHDL Issues for FPGA Design
        4.9 Summary

    Section 2: Applications

      Chapter 5: Introduction

      Chapter 6: Images and High Speed Processing
        6.1 Introduction
        6.2 The Camera Link Interface
        6.3 Getting Started
        6.4 Specifying the Interfaces
        6.5 Defining the Top Level Design
        6.6 System Block Definitions and Interfaces
        6.7 The CameraLink Interface
        6.8 The Hard Disc Interface
        6.9 Summary
      Chapter 7: Embedded Processors
        7.1 Introduction
        7.2 A Simple Embedded Processors
        7.3 Soft Core Processors on an FPGA
        7.4 Summary

    Section 3: Designer's Toolbox

      Chapter 8: Serial Communications
        8.1 Introduction
        8.2 Manchester Encoding and Decoding
        8.3 NRZ (Non-Return-to-Zero) Coding and Decoding
        8.4 NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding
        8.5 RS-232
        8.6 USB (Universal Serial Bus)
        8.7 Summary
      Chapter 9: Digital Filters
        9.1 Introduction
        9.2 Converting S Domain to Z Domain
        9.3 Implementing Z Domain Functions in VHDL
        9.4 Basic Low Pass Filter Model
        9.5 Finite Impulse Response (FIR) Filters
        9.6 Infinite Impulse Response (IIR) Filters
        9.7 Summary
      Chapter 10: Secure Systems
        10.1 Introduction to Block Ciphers
        10.2 Feistel Lattice Structures
        10.3 The Data Encryption Standard (DES)
        10.4 Advanced Encryption Standard (AES)
      Chapter 11: Memory
        11.1 Introduction
        11.2 Modeling Memory in VHDL
        11.3 Read Only Memory (ROM)
        11.4 Random Access Memory (RAM)
        11.5 Synchronous RAM (SRAM)
        11.6 Summary
      Chapter 12: PS/2 Mouse Interface
        12.1 Introduction
        12.2 PS/2 Mouse Basics
        12.3 PS/2 Mouse Commands
        12.4 PS/2 Mouse Data Packets
        12.5 PS/2 Operation Modes
        12.6 PS/2 Mouse with Wheel
        12.7 Basic PS/2 Mouse Handler VHDL
        12.8 Modified PS/2 Mouse Handler VHDL
        12.9 Summary
      Chapter 13: PS/2 Keyboard Interface
        13.1 Introduction
        13.2 PS/2 Keyboard Basics
        13.3 PS/2 Keyboard Commands
        13.4 PS/2 Keyboard Data Packets
        13.5 PS/2 Keyboard Operation Modes
        13.6 Basic PS/2 Keyboard Handler VHDL
        13.7 Modified PS/2 Keyboard Handler VHDL
        13.8 Summary
      Chapter 14: A Simple VGA Interface
        14.1 Introduction
        14.2 Basic Pixel Timing
        14.3 Image Handling
        14.4 VGA Interface VHDL
        14.5 Horizontal Sync
        14.6 Vertical Sync
        14.7 Horizontal and Vertical Blanking Pulses
        14.8 Calculating the Correct Pixel Data
        14.9 Summary

    Section 4: Optimizing Designs

      Chapter 15: Advanced Techniques
        15.1 Introduction
      Chapter 16: Synthesis
        16.1 Introduction
        16.2 VHDL Supported in RTL Synthesis
        16.3 Some Interesting Cases Where Synthesis May Fail
        16.4 What is Being Synthesized?
        16.5 Summary
      Chapter 17: Behavioral Modeling in VHDL
        17.1 Introduction
        17.2 How to Go from RTL to Behavioral VHDL
        17.3 Summary
      Chapter 18: Design Optimization
        18.1 Introduction
        18.2 Techniques for Logic Optimization
        18.3 Improving Performance
        18.4 Critical Path Analysis
        18.5 Summary
      Chapter 19: VHDL-AMS
        19.1 Introduction
        19.2 Introduction to VHDL-AMS
        19.3 Analogue Pins – Terminals
        19.4 Mixed Domain Modeling
        19.5 Analogue Variables – Quantities
        19.6 Simultaneous Equations in VHDL-AMS
        19.7 A VHDL-AMS Example – A DC Voltage Source
        19.8 A VHDL-AMS Example – Resistor
        19.9 Differential Equations in VHDL-AMS
        19.10 Mixed Signal Modeling with VHDL-AMS
        19.11 A Basic Switch Model
        19.12 Basic VHDL-AMS Comparator Model
        19.13 Multiple Domain Modeling
        19.14 Summary
      Chapter 20: Design Optimization Example: DES
        20.1 Introduction
        20.2 The Data Encryption Standard (DES)
        20.3 Moods
        20.4 Initial Design
        20.5 Initial Synthesis
        20.6 Optimizing the Datapath
        20.7 Final Optimization
        20.8 Results
        20.9 Triple DES
        20.10 Comparing the Approaches
        20.11 Summary

    Section 5: Fundamental Techniques

      Chapter 21: Counters
        21.1 Introduction
        21.2 Basic Binary Counter
        21.3 Synthesized Simple Binary Counter
        21.4 Shift Register
        21.5 The Johnson Counter
        21.6 BCD Counter
        21.7 Summary
      Chapter 22: Latches, Flip-Flops and Registers
        22.1 Introduction
        22.2 Latches
        22.3 Flip-Flops
        22.4 Registers
        22.5 Summary
      Chapter 23: Serial to Parallel & Parallel to Serial Conversion
        23.1 Serial to Parallel Conversion (SIPO)
        23.2 Parallel to Serial Conversion (PISO)
        23.3 Summary
      Chapter 24: ALU Functions
        24.1 Introduction
        24.2 Logic Functions
        24.3 1 Bit Adder
        24.4 Structural N-Bit Addition
        24.5 Configurable N-Bit Addition
        24.6 Twos Complement
        24.7 Summary
      Chapter 25: Decoders and Multiplexers
        25.1 Decoders
        25.2 Multiplexers
        25.3 Summary
      Chapter 26: Finite State Machines in VHDL
        26.1 Introduction
        26.2 State Transition Diagrams
        26.3 Implementing Finite State Machines in VHDL
        26.4 Summary
      Chapter 27: Fixed Point Arithmetic in VHDL
        27.1 Introduction
        27.2 Basic Fixed Point Types
        27.3 Fixed Point Functions
        27.4 Testing the Fixed Point Function
        27.5 Summary
      Chapter 28: Binary Multiplication
        28.1 Introduction
        28.2 Basic Binary Multiplication
        28.3 VHDL Unsigned Multiplier
        28.4 Synthesis of the Multiplication Function
        28.5 “Simple” Multiplication
        28.6 Summary
      Chapter 29: Bibliography
        29.1 Introduction
        29.2 Useful Texts for VHDL and FPGA Designers

This product was added to our catalog on Friday 26 October, 2007.


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