A unique and powerful RTOS designed exclusively for Microchip's PIC24 and dsPIC micro-controllers.
This pre-emptive, deterministic, multitasking, hard real-time kernel and innovative RTOS is designed exclusively for Microchip's PIC24 and dsPIC microcontrollers. Using an assembly instruction only found in the PIC24 and dsPIC, AVA finds the highest-priority task in only one clock cycle!
Note: The price on the upper right corner of this page is for the Seat License (single) only.
AVA RTOS Microchip PIC24 and dsPIC Features
- Manages an unlimited number of tasks
- Task require 19 bytes of RAM, excluding stack space
- 16 levels of priority
- Tasks at the same level are scheduled in a round-robin fashion
- Finds highest priority task in one instruction cycle
- O(1) scheduler
- Kernel requires less than 1.5k bytes of ROM
- ANSI C Compliant
AVA RTOS Microchip PIC24 and dsPIC Fundamental Tools
A Task is an execution context. It is used to execute a sequence of instructions in a mutually exclusive context.
An Event Group encapsulates 16 individual events. Each event is represented by a bit. An event can be used by your program to indicate when something has happened.
A task can either get or watch an event or combination of events. Both operations cause it to block if all the events are not set when invoked. Getting event(s) clears them after they are set. Watching events simply wakes up the task but does not clear the events.
An Interrupt Queue is used to pass byte oriented data between an Interrupt Service Routine and a task, or vice versa, in a synchronized manner. It uses an event, from an Event Group, to indicate whenever a write operation is performed on the Queue. This allows a task to wait on the event and process its contents as soon as an ISR is done writing to it.
A semaphore is a general purpose synchronization primitive used in all Operating Systems. It can be used to protect a critical region or manage access to a resource.
A lock is a synchronization mechanism used to protect a resource from concurrent access. It also employs a Priority Inheritance protocol to reduce Priority Inversion. Priority Inversion is when a lower priority task is accessing a resource that a higher priority task is waiting on.
A Memory Pool is a fixed memory block management mechanism. Allocating and releasing of memory blocks is performed in constant time and no extra overhead is required for each block of memory in the pool.
A Pipe is a inter-task communication mechanism. It employs a First-In First-Out data structure. Each slot in the pipe is designed to store an address to a much larger memory block allocated from a memory pool. A write operation will block if no slots are available. A read operation blocks if the pipe is empty.
A Synchronization Point is a run-time synchronization mechanism. A task or group of tasks can wait on a Synchronization Point for another task to wake them up. It is used to control task execution.
A Timer is a cyclic timer that sets an event on every period.
AVA RTOS Microchip PIC24 and dsPIC Related Links
A Seat License allows a single user to embed the AVA RTOS in an unlimited number of end products. A Seat License is not transferable.
A Site License allows you to the AVA RTOS into any end-products as long as the products are designed from a single site. You can manufacture an unlimited number of units of these products from any location worldwide.
A site is defined as a physical location: a building or series of related buildings within a 2-mile radius. Multiple Site Licenses are required if a company has multiple design facilities. A Site License is not transferable.