The LAP-F1 series of logic and protocol analyzers is for high-speed, comprehensive measurements. They provide a high sample rate, deep memory and a large number of channels in a single instrument. The hardware features a Xilinx high-performance FPGA chip and exclusive active probes that enhance sampling accuracy and stability. It includes an extensive protocol library of more than 110 built-in decoders, and straightforward software provides for efficient debugging. This hardware is optimized for complex circuits with high-frequency signals. It features a DSO connection and six hardware protocol triggers: I2C, I2S, SPI, SVID, UART, and CAN 2.0B. The active probes provide good impedance matching, reduced crosstalk and noise, and reinforced ground to enhance measurement quality and to provide accuracy and stability with high-speed signals. They support DUT bandwidths of up to 200 MHz. Four types of probes are available. With your purchase you will receive a complete set of two types of your choice (general-purpose, low-voltage, or negative-logic) and four eMMC probes. Whichever type you don't choose still can be purchased separately. See the bottom of this page for a feature comparison of the different probe types, the set selector, and links to individual extra probes. The eMMC probes allow you to use the eMMC5.1/SD3.0 Trigger feature of the analyzer, which by default is limited to four channels. There is an optional eMMC license that will allow you to trigger and decode all eMMC5.1/SD3.0 signals. That option includes 28 additional eMMC probes. LAP-F1 Series Features There are 10 different models in the LAP-F1 series. The first couple rows of the table below highlight the differences between them so you can choose the model that best suits your needs. Items / Type | LAP-F1404M | LAP-F1408M | LAP-F14016M | LAP-F14032M | LAP-F14064M | LAP-F1644M | LAP-F1648M | LAP-F16416M | LAP-F16432M | LAP-F16464M | Channels | 40 | 40 | 40 | 40 | 40 | 64 | 64 | 64 | 64 | 64 | Memory depth per channel | 4 Mbits | 8 Mbits | 16 Mbits | 32 Mbits | 64 Mbits | 4 Mbits | 8 Mbits | 16 Mbits | 32 Mbits | 64 Mbits | Memory depth / channels when using Channel Folding | 4Mb / 40 ch 8Mb / 16 ch 16Mb / 8 ch 32Mb / 4 ch 64Mb / 2 ch 128Mb / 1 ch | 8Mb / 40 ch 16Mb / 16 ch 32Mb / 8 ch 64Mb / 4 ch 128Mb / 2 ch 256Mb / 1 ch | 16Mb / 40 ch 32Mb / 16 ch 64Mb / 8 ch 128Mb / 4 ch 256Mb / 2 ch 512Mb / 1 ch | 32Mb / 40 ch 64Mb / 16 ch 128Mb / 8 ch 256Mb / 4 ch 512Mb / 2 ch 1Gb / 1 ch | 64Mb / 40 ch 128Mb / 16 ch 256Mb / 8 ch 512Mb / 4 ch 1Gb / 2 ch | 4Mb / 64 ch 8Mb / 32 ch 16Mb / 16 ch 32Mb / 8 ch 64Mb / 4 ch 128Mb / 2 ch 256Mb / 1 ch | 8Mb / 64 ch 16Mb / 32 ch 32Mb / 16 ch 64Mb / 8 ch 128Mb / 4 ch 256Mb / 2 ch 512Mb / 1 ch | 16Mb / 64 ch 32Mb / 32 ch 64Mb / 16 ch 128Mb / 8 ch 256Mb / 4 ch 512Mb / 2 ch 1Gb / 1 ch | 32Mb / 64 ch 64Mb / 32 ch 128Mb / 16 ch 256Mb / 8 ch 512Mb / 4 ch 1Gb / 2 ch | 64Mb / 64 ch 128Mb / 32 ch 256Mb / 16 ch 512Mb / 8 ch 1Gb / 4 ch | Operating System | Windows 8.1 (recommended), Windows 7, Windows Vista, Windows XP, Windows 2000 — (32- or 64-bit versions supported) | Transmission | USB 3.0 (2.0 compatible) | Sample rate | Internal (timing) max | 1 GHz | External (state) max | 32 | Trigger | Trigger Channels | 32 (channels divided into 2 groups; or triggering between 1st group (32 ch) and 2nd group (8/32 ch) | Trigger Events | Pattern / Edge / Pulse-width / Interval (time) | Trigger Delay | Yes | Trigger Sequence | 256 Levels | Trigger Pass | 1 to 65535 | Trigger Voltage | 4 simultaneous levels; 1 for each of the 4 ports | Auxiliary Cursors | 250 | Hardware Triggers | I2C, I2S, SPI, SVID, UART, CAN 2.0B | eMMC5.1/SD3.0 Trigger | 4 ch. can be triggered/sampled/decoded at 2GHz in standard package; see Optional Functions below for details about getting full support | Software Functions | Languages | English, Simplified Chinese, Traditional Chinese | Zooming & Panning | 2 cursor modes | Waveform & UI Customization | Modify appearance of channels, menus, traces, windows, etc. | State List & Waveform View | Present samples as list of 1s and 0s, or as waveform | DSO Connection | Connect to and import signals from DSOs | File Comparison | Compare 2 files to see where and how they differ | Navigator | Quickly navigate to distant parts of the waveform | Memory View | See what the memory looks like; what is read/written to which address | Packet List | Breakdown of all packets in list form | Statistics | Table view showing number of periods, periods that satisfy conditions, etc. | Real-time Signal Activity | Live view of probe activity | Protocol Decoders | More than 110 free built-in protocol decoders | Phase Errors | Less than 3ns | Power | AC in: 100-240V @ 50/60Hz; DC out: 9V/5.55A | Dimensions | 322 × 180 × 38 mm | Certifications | CE, FCC | Optional Functions | Channel Folding | As seen above, you can activate this free option to give your LAP-F1 unit the ability to concentrate the total memory on a limited number of channels. For example, with this 64-channel version with 8Mb per channel, you could enable only 32 channels to get 16Mb per channel, or enable only 16 channels to get 32Mb per channel, etc. | eMMC5.1/SD3.0 | Purchase this option to unlock 32-channel 2GHz sampling and the ability to trigger and decode all signals of eMMC5.1/SD3.0. An additional 28 probes are included with purchase of this option, to give you a total of 32. As eMMC has only 11 signals, the remaining signals can be used for other high-speed acquisitions. | Long-time Record | Firmware option (separate purchase) to unlock the ability to stream samples directly to disk. Up to 64 channels can be streamed at an average rate of 300MB/s using USB 3.0. The long-time record function can be used to acquire signals from 7 hours up to a month depending on your sampling setup. Note that a fairly powerful PC is required to run this function reliably. | Built-in protocols The LAP-F1 series can decode the following protocols right out of the box: - Automotive — CAN 2.0B, DSI Bus, FlexRay 2.1A, LIN 2.1, MVB, WTB
- PC System — FWH, GPIB, Low Pin Count, LPC-SERIRQ, LPT, PCI, PECI, PS/2, SVID, USB 1.1, USB 2.0
- Memory — Compact Flash 4.1, I2C (EEPROM 24L), I2C (EEPROM 24LCS61/24LCS62), MICROWIRE (EEPROM 93C), SD2.0/SDIO, SAMSUNG K9 (NAND Flash), SPI Compatible (Atmel Memory), UNI/O
- Digital Audio — AC97, DSA Interface, HD Audio, HDMI CEC, I2S, MIDI, PCM, PSB Interface, S/PDIF, STBus
- IC Interface — 1-WIRE, 1-Wire (Advanced), 3-WIRE, BDM, HPI, I2C, JTAG 2.0, MCU-51 DECODE, MICROWIRE, SLE4442, SSI Interface, ST7669, SPI, SPI PLUS, Serial Wire Debug (SWD), UART (RS-232C/422/485)
- Basic Logic Application — ARITHMETICAL LOGIC, DIGITAL LOGIC, JK FLIP-FLOP, UP DOWN COUNTER
- Infrared Rays — IRDA, NEC PD6122, Philips RC-5, Philips RC-6, PT2262/PT2272
- Optoelectronics — 7-SEGMENT LED, CCIR656, CMOS IMAGE, DALI Interface, DM114/DM115, DMX512, LCD12864, LCD1602, LG4572, S2Cwire/AS2Cwire, SCCB
- Power — BMS, HDQ, PMBus 1.1, SDQ, SMBus 2.0
- Wireless — Differential Manchester, DigRF, ISO7816 UART, KEELOQ Code Hopping, MANCHESTER, MII, MILLER, MIL-STD-1553, MODIFIED MILLER, SIGNIA 6210, SWP, WIEGAND, WWV/WWVH/WWVB
- Other — DS1302, DS18820, HART, KNX, ModBus, MODIFIED SPI, OPENTHERM 2.2, PROFIBUS, SHT11, YK-5
LAP-F1 64-channel Series Package Contents - LAP-F1 logic analyzer hardware
- CD with software and user manual
- 32 probes (two channels per probe)
- Four eMMC probes
- One eMMC Clock-In probe
- 37 USB 3.0 cables for connection to probes, A-to-A type, 32.5 cm
- 64 signal/ground cable pairs, 7.5 cm
- 128 clip-on connectors
- USB 3.0 cable for connection to PC, A-to-B type, 1.5 m
- 9V power supply with detachable 1.8 m cable
- BNC cable, 1 m
- UTB300 Combo PCI-e 4x card to give your PC two USB 3.0 ports and two SATA-III ports
The active probes connect to LAP-F1 via USB 3.0. The ports are separated into four groups of eight channels: A0-A7, B0-B7, C0-C7 and D0-D7. Independent trigger voltage levels can be set for each of the four groups. The probes are colored and numbered and it is recommended to follow the color codes when setting up the instrument. Probe Specifications The following table shows the specifications for the different probe types. A complete set of P120LV Low Voltage Probes probes and four P200EM eMMC/SD probes are included with your purchase. If you order the optional eMMC5.1/SD3.0 Full Software License you will receive 28 additional eMMC/SD Probes for a total of 32Note: The P120LV probes included can operate within the same voltages as the P100ST. Model Name | P100ST (General Purpose) | P120LV (Low Voltage) | P120NE (Negative Logic) | P200EM (eMMC/SD) | Included in base purchase | Yes, if chosen below | Yes, if chosen below | Yes, if chosen below | 4 included in base purchase | Signal type | Single-ended bus | Single-ended bus | Single-ended bus | Single-ended bus | Channels (max) | 64 | 64 | 64 | 32 | Input Impedance / Capacitance | 530 kOhm ±10% 8.2pF ±2pF | 190 kOhm ±10% 4.3pF ±2pF | 190 kOhm ±10% 4.3pF ±2pF | 190 kOhm ±10% 4.3pF ±2pF | DUT Bandwidth (max) | 100 MHz | 120 MHz | 120 MHz | 200 MHz | Transmission Rate (max) | 100 Mbit/s | 120 Mbit/s | 120 Mbit/s | 400 Mbit/s | Trigger Voltage | User defined | User defined | User defined | User defined | Bus Voltage | VIH: 2V to 5V | VIH: 0.6V to 5V | VIH: 0.3V to 5V or VIH: -0.2V to -1.5V | VIH: 0.6V to 5V | Input Signal Level | -5V to +5V | 0V to 5V | -5V to +5V | 0V to 5V | Input DC Voltage (max) | ±5V | ±10V | ±10V | ±10V | LAP-F Series Logic Analyzer Resources
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