The J-Link ULTRA+ is an enhanced version of the J-Link ULTRA JTAG In-Circuit Debugger/Programmer. This version includes integrated licenses for the J-Flash software, the RDI Interface software, and the Flash Breakpoints component. Thus you save over $1100 off the cost of purchasing each component separately! J-Link ULTRA+ is a JTAG/SWD emulator designed for ARM/Cortex and other supported CPUs. It is fully compatible to the standard J-Link and works with the same PC software, but offers even higher speed as well as target power measurement capabilities due to the faster CPU, built-in FPGA and High-Speed USB interface. View J-Link ULTRA Speed Demonstration. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. J-Link ULTRA+ has a built-in 20-pin JTAG/SWD connector. Adapter cables are available for other programming interfaces. J-Link ULTRA+ Features - Supported CPUs: Any ARM7/9/11, Cortex-A5/A8/A9, Cortex-M0/M1/M3/M4, Cortex-R4, RX610, RX621, RX62N, RX62T, RX630, RX631, RX63N
- Download speed up to 3 MBytes per second
- High-speed USB 2.0 interface
- Serial Wire Debug (SWD) support
- Serial Wire Viewer (SWV) support
- SWV: UART and Manchester encoding supports
- SWO sampling frequencies up to 25 MHz
- Target power supply: J-Link can supply up to 300 mA to target with overload protection
- Target power consumption can be measured with high accuracy
- Direct download into Flash memory of most popular microcontrollers supported
- Automatic core recognition
- JTAG speed up to 60 MHz
- Supported by all major IDEs such as IAR EWARM, Keil MDK, Rowley CrossWorks, Atollic TrueSTUDIO, IAR EWRX, Renesas HEW, Renesas e2studio, etc.
- No power supply required; powered through USB
- Support for adaptive clocking
- All JTAG signals can be monitored; target voltage can be measured
- Supports concurrent access to CPU by multiple applications (see below)
- Cross-platform support (limited use on Linux and Mac; see below)
- Intelligence in the emulator firmware (communication handled on the J-Link — not on the PC side)
- Remote Server included (allows using J-Link remotely via TCP/IP)
- GDB Server included (see below for details)
- Supports multiple target interfaces: JTAG, SWD
- Supports SWV/SWO (Serial Wire Viewer / Serial Wire Output)
- Wide target voltage range: 1.2V - 3.3V, 5V tolerant
- Supports JTAG chains with multiple devices
- Embedded Trace Buffer (ETB) support
- Fully plug-and-play compatible
- Standard 20-pin JTAG connector
- USB and 20-pin ribbon cable included
- Optional Software Developer Kit (SDK) available
- Optional Adapters available for 14-pin ARM, 14-pin TI OMAP, 9-pin and 19-pin Cortex-M, and Renesas RX micros
- Optional optical isolation adapter available
J-Link allows multiple applications to have access to the CPU at the same time. This has numerous advantages. For example: J-Link Commander can be used in parallel with a debugger; a tool to communicate via DCC can be used in parallel with a debugger; or a visualization tool such as Micrium's u/C-Probe or Segger's kernel viewer embOSView. (This feature currently is not available for Cortex-A or Cortex-R cores.) On Mac and Linux, only the following components are supported: J-Link Commander, command-line GDB Server, shared library (DLL equivalent). Download J-Link Documentation J-Link Software In additional to the larger software components mentioned in detail on this page, the following free software tools are included in the J-Link software package: J-Link Configurator is a utility to manage multiple J-Links connected to the PC via USB or Ethernet. J-Link Commander is a simple command-line utility primarily for diagnostics and troubleshooting. J-Link Remote Server allows a J-Link to be used remotely via TCP/IP. This enables you to connect to and fully use a J-Link from another computer. Performance is just slightly (about 10%) lower than with direct USB connection. SWO Viewer shows terminal output of the target perfomed via SWO pin. J-Mem displays memory contents of ARM systems and allows modifications of RAM and sfrs (special function registers) while the target is running. This makes it possible to look into the memory of an ARM chip at run time; RAM can be modified and sfrs can be written. The type of access for both read and write can be selected to be 8/16/32-bit. It works nicely when modifying sfrs, especially because it writes the sfr only after the complete value has been entered. J-Link DLL Updater makes sure you have the latest DLL which allows third-party applications to use the J-Link. Dedicated flash programming utilities (DFPU) for a number of popular evaluation boards. Download J-Link Software  J-Link GDB Server The J-Link GDB Server translates the monitor commands from your GDB-capable Integrated Development Environment into commands understood by the J-Link ARM. As such it allows you to use the J-Link with any ARM Toolchain and IDE that supports GDB. It supports transfer of SWO data (terminal output, instrumentation trace, PC samples, etc.). User interface The J-Link GDB Server's graphical user interface shows information about the debugging process and the target connected via JTAG, including: - Host IP address that is connected to the J-Link GDB Server
- Connection status of J-Link
- Information about the target core
- Measured target voltage
- Bytes that have been downloaded
- Status of target
- Log output of the J-Link GDB Server (if Log window is checked)
- Initial and current JTAG speed
- Target endian setting
There also is a command-line version available for Linux, Mac and Windows. Supported cores Currently the J-Link GDB Server can be used with the following CPU cores: ARM7, ARM9, ARM11, Cortex-A5, Cortex-A8, Cortex-A9, Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-R4, RX610, RX621, RX62N, RX62T, RX630, RX631, RX63N. Supported remote commands J-Link GDB Server supports several remote commands from the GDB. These commands can be used from within a .gdbinit file or the GDB console to initialize the target board and to set up J-Link GDB Server specific parameters.
| Command | Function | | ClrBP | Removes an instruction breakpoint. | | Endian | Sets endianess of the target. | | Go | Starts the target CPU. | | Halt | Halts the target CPU. | | JTAGConf | Configures a JTAG scan chain with multiple devices on it. | | Long | Reads or writes from/to given address. | | Reg | Reads or writes from/to given register. | | Reset | Resets and halts the target CPU. | | Select | Selects the way J-Link is connected to host system. | | SetBP | Sets an instruction breakpoint at a given address. | | Sleep | Sleeps for a given time period. | | Speed | Sets the JTAG speed of J-Link / J-Trace. | | Step | Performs one or more single instruction steps. | | WaitHalt | Waits for target to halt code execution. | | WIce | Writes to given IceBreaker register. | J-Flash ARM Software J-Flash is a software application for Windows systems which enables you to program your Flash EEPROM devices via the On-Chip Debug connector (JTAG) on your target system, when used with the J-Link. View J-Flash Introduction Video. J-Flash works with any ARM system and supports all common external Flash devices, as well as the programming of internal Flash in ARM microcontrollers. It allows you to ERASE, FILL, Program BLANK CHECK, CHECKSUM, UPLOAD Flash content, and VIEW MEMORY functions of the software with your Flash devices. J-Flash Programming Software Features - Works with any ARM7/9/11 and Cortex-M0/M3 core
- Supports internal Flash of most popular microcontrollers
- Supports CFI-compliant NOR flash (combinations 18x, 2x8, 1x16, 2x16)
- Supports most non-CFI compliant NOR flash devices (combinations 18x, 2x8, 1x16, 2x16)
- Can support SPI NOR-Flash, NAND Flash, and Atmel DataFlash (see note below)
- Multi-bank programming support (only with Flasher-ARM hardware in standalone mode)
- High-speed programming: up to 150 kByte/sec (depending on device)
- Very high blank-check speed: Approx. 16 Mybtes/sec (depending on target)
- Smart read-back: Only non-blank portions of Flash transferred and saved
- Easy to use; comes with projects for standard eval boards
After installing the J-Link driver and J-Flash, simply connect your J-Link to your PC and start the J-Flash executable. Project files for common CPUs and Eval boards are provided. If you do not find an existing project file for your selected CPU, it is easy to write and save your own project file: Simply choose Option|Project from the Menu and select the right settings for your target hardware. Support for Atmel DataFlash, NAND Flash, SPI-NOR Flash Since the connection of these Flashes varies from microcontroller to microcontroller, there are always some modifications which are necessary to get DataFlash/NAND/SPI-NOR Flash supported on a specific hardware. The J-Flash software comes with sample projects which allow programming the DataFlash/NAND Flash on popular evaluation boards. If you have a hardware design which is based on one of these eval boards, these sample projects should work for your hardware also. If your hardware design varies too much, then a custom RAMCode will be needed to program the Flash of your target hardware. A RAMCode template is available to help you write your own. J-Flash Programming Software Supported Devices J-Flash can program external as well as internal Flash. Any combination of ARM CPU and external Flash is supported if the Flash chip is in the complete lists of supported microcontrollers and external Flash devices. As well as the listed Flash chips, every CFI-compliant chip is supported. In addition, all types of Flash interfacing are supported: 1 x 8-bit, 2 x 8-bit, 4 x 8-bit, 1 x 16-bit, 2 x 16-bit, 1 x 32-bit. Download J-Flash User Manual J-Link RDI Interface The J-Link RDI interface makes it possible to use the J-Link ULTRA+ with any RDI-compliant debugger. The package consists of two DLLs which need to be copied to the debugging software's program folder and selected in your debugger software. The following RDI-compliant debuggers have been tested with J-Link RDI: ARM Developer Suite (ADS), ARM RealView Development Suite (RVDS) V3.0 (not V3.1 or above as RDI support has been withdrawn), IAR Embedded Workbench for ARM (EWARM), and RealView MicroController Development Kit (Keil MDK). J-Link RDI Software Configuration RDI allows various configuration settings, such as - Target system initialization via setup file
- JTAG Speed and scan chain settings
- Enable / disable Flash programming
- Breakpoint settings (use software breakpoints; use Flash breakpoints
- CPU-specific settings (Endianness; Reset strategy)
Normally, the default settings can be used. The Speed field allows the selection of a fixed JTAG speed. Via setup file, the target system can be initialized in just about any way required. Setup File Commands: | SetJTAGSpeed(x); | Sets the JTAG speed, x = speed in kHz (0=Auto) | | Delay(x); | Waits a given time,
x = delay in milliseconds | | Reset(x); | Resets the target,
x = delay in milliseconds | | Go(); | Starts the ARM core | | Halt(); | Halts the ARM core | | Read8(Addr); | Reads a 8/16/32 bit value,
Addr = address to read (as hex value) | | Read16(Addr); | | Read32(Addr); | | Verify8(Addr, Data); | Verifies a 8/16/32 bit value,
Addr = address to verify (as hex value)
Data = data to verify (as hex value) | | Verify16(Addr, Data); | | Verify32(Addr, Data); | | Write8(Addr, Data); | Writes a 8/16/32 bit value,
Addr = address to write (as hex value)
Data = data to write (as hex value) | | Write16(Addr, Data); | | Write32(Addr, Data); | | WriteVerify8(Addr, Data); | Writes and verifies a 8/16/32 bit value,
Addr = address to write (as hex value)
Data = data to write (as hex value) | | WriteVerify16(Addr, Data); | | WriteVerify32(Addr, Data); | | WriteRegister(Reg, Data); | Writes a register | | WriteJTAG_IR(Cmd); | Writes the JTAG instruction register | | WriteJTAG_DR(nBits, Data); | Writes the JTAG data register | Example setup file: /*********************************************************************
*
* Setup file for J-LINK RDI
*
**********************************************************************
* File: LPC2294.setup
* Purpose: Setup for Philips LPC2294 chip
**********************************************************************
*/
SetJTAGSpeed(1000);
Reset(0);
Write32(0xE01FC040, 0x00000001); // Map User Flash into Vector area at (0-3f)
Write32(0xFFE00000, 0x20003CE3); // Setup CS0
Write32(0xE002C014, 0x0E6001E4); // Setup PINSEL2 Register
SetJTAGSpeed(2000);
Download J-Link RDI User Manual Flash Breakpoints License The Flash Breakpoints license allows you to set an unlimited number of software breakpoints in Flash memory areas, rather than just the 2 hardware breakpoints. A RAM code, specially designed for this purpose, sets and clears Flash breakpoints extremely fast; on micros with fast Flash the difference between breakpoints in RAM and Flash is hardly noticeable. In addition, a combination of software and hardware breakpoints, as well as a built-in instruction set simulator, reduces the number of Flash operations that need to be performed. This minimizes delays for the user, maximizing the lifetime of the Flash. All resources of the ARM micro are available to the application program; no memory is lost for debugging. View Flash Breakpoints Demonstration. Download Comparison Sheet to see the differences between the various J-Link and J-Trace models. Ships from: USA
Leadtime: In stock
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