MIPS RISC Architecture, 2nd edition, is a complete reference manual about the MIPS RISC architecture. Authors Gerry Kane and Joe Heinrich describe the Instruction Set Architecture (ISA) used by the R2000, R3000, R4000, and R6000 (collectively known as the R-Series) processors, together with an extension to this ISA. Focusing on the new R4000 and R6000 chips, this book is organized into two major sections: Chapters 1 through 6 describe the characteristics of the CPU, while Chapter 7 through 9 describe the Floating Point Unit (FPU). This book describes the general characteristics and capabilities of each RISC processor, along with a description of the programming model, memory management unit (MMU), and the registers associated with each processor. Also included is an overview of the underlying concepts that distinguish RISC architecture from Complex Instruction Set Computer (CISC) architecture. 544 pages, softcover Contents - 1. RISC Architecture: An Overview
- 2. MIPS Processor Architecture Overview
- 3. CPU Instruction Set Summary
- 4. Memory Management System
- 5. Caches
- 6. Exception Processing
- 7. FPU Overview
- 8. FPU Instruction Set Summary and Instruction Pipeline
- 9. Floating-Point Exceptions
- A. CPU Instruction Set Details
- B. FPU Instruction Set Details
- C. Machine Language Programming Tips
- D. Assembly Language Programming
- E. IEEE Standard 754 Floating-Point Compatibility Issues
- F. Scheduling Hazards
- Index
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