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AM3359 Cortex-A8 CPU Module, Dual 2x40-pin 0.4mm-pitch Headers US$109.00

AM3359 Cortex-A8 CPU Module, Dual 2x40-pin 0.4mm-pitch Headers

Measuring only 60mm by 27mm, the Mini8600B processor card is a small form-factor controller board with TI's AM3359 ARM Cortex-A8 processor. The tiny module integrates 2256MBytes DDR3 SDRAM and 512Mbytes NAND Flash and uses two 0.4mm-space 240-pin board-to-board male expansion connectors to bring out many hardware peripheral signals and GPIOs from the CPU.

A complete, ready-to-run Linux/Android/WinCE development board with this CPU module is available: The SBC8600B.

AM3359 CPU Module Features

  • TI AM3359 ARM Cortex-A8 720MHz 32-bit RISC CPU with NEON SIMD Coprocessor, 32KB/32KB of L1 Instruction/Data Cache with Single-Error Detection (parity), 256KB of L2 Cache with Error Correcting Code (ECC), SGX530 Graphics Engine, and Programmable Real-Time Unit Subsystem
  • 2256MB DDR3 SDRAM (on Mini8600B CPU board)
  • 512MB NAND Flash (on Mini8600B CPU board
  • Dimensions: 60 27 mm (8-layer PCB design)
  • Temperature Range: 0 to 70 C
  • Humidity Range: 20% to 90%
  • Input Voltage: 3.3V

Expansion Interfaces and Signals Routed to Pins

Two 240-pin, 0.4mm-pitch board-to-board male expansion connectors provide:
  • TFT LCD interface (supports 24-bpp parallel RGB interface LCD)
  • Two USB2.0 OTG ports with integrated PHY, High-Speed
  • Three inter-integrated circuit (I2C) bus interfaces
  • Six UART interfaces
  • One SPI interface
  • Two 10/100/1000 Mbps Ethernet MAC (EMAC) with Management Data Input/Output (MDIO) module
  • Multichannel audio serial port (McASP)
  • 8-channel 12-bit ADC interface
  • Two 4-line SD/MMC card interfaces
  • GPMC bus

Pin Signal Description Pin Signal Description
2VDDS_RTCSupply voltage for RTC 2GNDGND
3CLK_OUT1Clock Out 1 3MCASP0_AHCLKXMCASP0 transmit master clock
4CLK_OUT2Clock Out 2 4MCASP0_ACLKXMCASP0 transmit bit clock
5MMC0_DAT0MMC0 data bus 5MCASP0_FSXMCASP0 transmit frame sync
6MMC0_DAT1MMC0 data bus 6MCASP0_AXR0MCASP0 serial data (I/O)
7MMC0_DAT2MMC0 data bus 7MCASP0_AHCLKRMCASP0 receive master clock
9MMC0_DAT3MMC0 data bus 9MCASP0_FSRMCASP0 receive frame sync
10AM335X_PWRON_RESETNCPU PWRON reset 10MCASP0_AXR1MCASP0 serial data (I/O)
13AM335X_PRU_UART0_CTSPRU UART0 Clear To Send 13VDDA_ADCSupply voltage range for ADC
14AM335X_PRU_UART0_RXPRU UART0 receive data 14AM335X_ADC0ADC0
15AM335X_PRU_UART0_RTSPRU UART0 Request To Send 15AM335X_ADC1ADC1
16AM335X_PRU_UART0_TXPRU UART0 transmit data 16AM335X_ADC2ADC2
17AM335X_UART0_RXUART0 receive data 17AM335X_ADC3ADC3
18AM335X_UART3_RXUART3 receive data 18AM335X_ADC4ADC4
19AM335X_UART0_TXUART0 transmit data 19AM335X_ADC5ADC5
20AM335X_UART3_TXUART3 transmit data 20AM335X_ADC6ADC6
21AM335X_CAN0_RXCAN0 receive data 21AM335X_ADC7ADC7
22AM335X_I2C0_SDAI2C0 master serial data 22GND_ADCGND ADC
23AM335X_CAN0_TXCAN0 transmit data 23GNDGND
24AM335X_I2C0_SCLI2C0 master serial clock 24GNDGND
25AM335X_UART4_RXUART4 receive data 25LCD_DATA1LCD data bus
26AM335X_UART1_RXUART1 receive data 26LCD_DATA12LCD data bus
27AM335X_UART4_TXUART4 transmit data 27LCD_DATA0LCD data bus
28AM335X_UART1_TXUART1 transmit data 28LCD_DATA10LCD data bus
29GNDGND 29LCD_DATA5LCD data bus
30GNDGND 30LCD_DATA13LCD data bus
31MII1_COLMII1 collision detect 31LCD_DATA4LCD data bus
32AM335X_USB0_DRVVBUSUSB0 controller VBUS control output 32LCD_DATA11LCD data bus
33MII1_TX_CLKMII1 transmit clock 33LCD_DATA6LCD data bus
34AM335X_USB1_DRVVBUSUSB1 controller VBUS control output 34LCD_DATA14LCD data bus
35MII1_TX_ENMII1 transmit enable 35LCD_DATA8LCD data bus
36MII1_REF_CLKMII1 reference clock 36LCD_VSYNCLCD vertical sync
37MII1_TXD3MII1 transmit data 37GNDGND
38MII1_CRSMII1 carrier sense 38GNDGND
39MII1_TXD2MII1 transmit data 39LCD_DATA9LCD data bus
40MII1_RX_ERMII1 receive data error 40LCD_PCLKLCD pixel clock
41MII1_TXD1MII1 transmit data 41LCD_DATA15LCD data bus
42MII1_RX_DVMII1 receive data valid 42GPMC_AD11GPMC address and data
43MII1_TXD0MII1 transmit data 43LCD_DATA3LCD data bus
44MII1_RX_CLKMII1 receive clock 44GPMC_AD15GPMC address and data
46MII1_RXD3MII1 receive data 46GPMC_AD14GPMC address and data
47MII_MDCMII MDIO clock 47LCD_DATA7LCD data bus
48MII1_RXD2MII1 receive data 48GPMC_WAIT0GPMC wait 0
49GNDGND 49LCD_HSYNCLCD horizontal sync
50MII1_RXD1MII1 receive data 50GPMC_BEN1GPMC byte enable 1
52MII1_RXD0MII1 receive data 52GNDGND
53AM335X_USB0_DPUSB0 DP 53LCD_ENLCD AC bias enable chip select
54MMC0_CMDMMC0 command signal 54GPMC_WPNGPMC write protect
55GNDGND 55GPMC_AD13GPMC address and data
56USB0_VBUSUSB0 bus voltage 56GPMC_CSN3GPMC chip select 3
57AM335X_USB1_DMUSB1 Data- 57GPMC_AD9GPMC address and data
58AM335X_USB1_IDUSB1 ID 58GPMC_CSN2GPMC chip select 2
59AM335X_USB1_DPUSB1 Data+ 59GPMC_AD10GPMC address and data
61GNDGND 61GPMC_AD8GPMC address and data
62USB1_VBUSUSB1 bus voltage 62GPMC_AD6GPMC address and data
63GPMC_A0GPMC address 63GPMC_AD12GPMC address and data
64GPMC_A7GPMC address 64GNDGND
65GPMC_A5GPMC address 65GNDGND
66GPMC_A11GPMC address 66GPMC_CSN1GPMC chip select 1
67GPMC_A4GPMC address 67GPMC_ADVN_ALEGPMC address valid / address latch enable
68GPMC_A10GPMC address 68GPMC_AD5GPMC address and data
69GPMC_A3GPMC address 69GPMC_BEN0_CLEGPMC byte enable 0 / command latch enable
70GPMC_A9GPMC address 70GPMC_AD4GPMC address and data
71GPMC_A2GPMC address 71GPMC_OEN_RENGPMC output / read enable
72GPMC_A8GPMC address 72GPMC_AD1GPMC address and data
73GPMC_A6GPMC address 73GPMC_AD2GPMC address and data
74GPMC_A1GPMC address 74GPMC_AD0GPMC address and data
75GNDGND 75GPMC_AD3GPMC address and data
76GNDGND 76GPMC_CSN0GPMC chip select 0
77VDD_3V3Power 77GPMC_AD7GPMC address and data
78VDD_3V3Power 78GPMC_WENGPMC write enable
79VDD_3V3Power 79GNDGND
80VDD_3V3Power 80GNDGND

AM3359 CPU Module Resources

Ships from: China
Lead time: 4 weeks

This product was added to our catalog on Wednesday 19 June, 2013.


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