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Samsung S5PV210 ARM Cortex-A8 Processor Card, 1GB DDR, 1GB Flash US$159.00

Samsung S5PV210 ARM Cortex-A8 Processor Card, 1GB DDR, 1GB Flash

The Embest Mini2100 processor card is features the Samsung S5PV210 ARM Cortex-A8 application processor which is powered by a 1GHz ARM Cortex-A8 core with built-in the programmable PowerVR SGX540 core. The board has 1Gbytes mobile DDR2 and 1Gbytes Nand Flash, and uses four 0.5mm-space 2×40-pin female board-to-board connectors to bring out many hardware peripheral signals and GPIOs from the CPU.

S5PV210 CPU Board Features

    Mechanical Specifications
  • Dimensions: 55.2mm × 50.5mm (8-layer PCB design)
  • Operating temperature: 0~70 Celsius
  • Humidity Range: 20% to 90%
  • Power Consumption: 200mA @ 5V
    Samsung S5PV210 Mobile Application Processor
  • Up to 1 GHz ARM Cortex-A8 Core with NEON; also supports 800 MHz operation
  • 32KB I-Cache; 32KB D-Cache; 512KB L2 Cache
  • On-chip 64KB ROM and 96KB SRAM
  • Built-in programmable PowerVR SGX540 core
  • 2D/3D Graphics Acceleration
  • Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p @ 30 fps and decoding of MPEG-2/VC1 video up to 1080p @ 30 fps
  • 1 GBytes Mobile DDR2, 8-bit
  • 1 GBytes NAND Flash, 8-bit
    Four 0.5mm-space 2×20-pin board-to-board female expansion connectors
  • TFT LCD Interface (support 24/ 18/ 16-bpp parallel RGB Interface LCD)
  • Analog TV interface (support NTSC / PAL)
  • HDMI Digital TV Interface (Supports 480p, 576p, 720p, 1080i, 1080p)
  • 3-channel Camera Interfaces (Supports ITU-R BT 601/656 YCbCr 8-bit, MIPI mode)
  • PCM Audio Interface (Supports three port PCM interface)
  • AC97 Audio Interface (Supports AC97 Full Specification)
  • JTAG Debugger Interface
  • USB 2.0 OTG (Supports high-speed up to 480 Mbps)
  • USB 2.0 Host (Supports high-speed up to 480 Mbps)
  • 14×8 Key Matrix support
  • 2-channel SPI Interfaces
  • 3-channel IIS bus interfaces
  • 3-channel IIC bus interfaces
  • 4 channel HS-MMC/SD
  • 4-channel UART (Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/ receive)
  • 10-channel multiplexed ADC (support Maximum 500Ksamples/sec and 12-bit resolution)
  • GPIO (up to 237 multi-functional input/ output ports)

Board connector pinouts

Note that the following tables are not a physical representation of each connector relative to each other. The orientation of each connector varies; Pin 1 is indicated by an arrow on the silkscreen.

CN1   CN2
Pin Signal Description Pin Signal Description
1XM0DATA1Memory port 0 Data Bit 1 1VDD_REG1_IO+3.3V
2XM0DATA10Memory port 0 Data Bit 10 2VDD_REG1_IO+3.3V
3XM0DATA13Memory port 0 Data Bit 13 3VDD_REG1_IO+3.3V
4XM0DATA2Memory port 0 Data Bit 2 4VDD_REG1_IO+3.3V
5XM0ADDR2Memory port 0 Address Bit 2 5VDD_REG1_IO+3.3V
6USERLED33SPI master output / slave input line for channel 0 6GNDGND
11L3DATASPI master input / slave output line for channel 0 11GNDGND
12CAM_B2_D3Camera data bit 3 12GNDGND
14XMMC1CMDCOMMAND/RESPONSE (SD/SDIO/MMC card interface channel 1) 14GNDGND
15XMMC1DATA3DATA3(SD/SDIO/MMC card interface channel 1) 15GNDGND
16XEINT23_HP_DECTECTSD_3_DATA[2](SD/SDIO/MMC card interface channel 3) 16CAM_B2_CLKOUTMODEM (MSM) IF Address(MSM_ADDR [13] should be '0')
18XMMC0DATA0DATA[0] (SD/SDIO/MMC card interface channel 0) 18GNDGND
19XMMC0DATA3DATA[3] (SD/SDIO/MMC card interface channel 0) 19GNDGND
20CAM_B2_D7Camera data bit 7 20GNDGND
22CAM_B2_HREFMODEM (MSM) IF Address(MSM_ADDR[13] should be ‘0’) 22VSYNC_LDIGPIO
23CAM_B2_FIELDMODEM (MSM) IF Address(MSM_ADDR[13] should be ‘0’) 23XjTCKXjTCK (TAP Controller Clock) provides the clock input for the JTAG logic.
Pull-down resistor is connected.
24CAM_B2_D4Camera data bit 4 24XI2CSDA0IIC-bus clock for channel 0
25CAM_B2_VSYNCMODEM (MSM) IF Address (MSM_ADDR[13] should be ‘0’) 25XjTDIXjTDI (TAP Controller Data Input) is the serial input for test instructions
and data. Pull-up resistor is connected.
26CAM_B2_D0Camera data bit 0 26XjTMSXjTMS (TAP Controller Mode Select) controls the sequence of the
TAP Controller’s states. Pull-up resistor is connected.
27CAM_B2_D5Camera data bit 5 27GNDGND
28XM0DATA9Memory port 0 Data Bit 9 28GNDGND
29GNDGND 29XadcAIN_4ADC Analog Input Bit 4
30XM0DATA11Memory port 0 Data Bit 11 30GNDGND
31XM0DATA8Memory port 0 Data Bit 8 31XadcAIN_6ADC Analog Input Bit 6
34GNDGND 34XadcAIN_7ADC Analog Input Bit 7
35GNDGND 35XadcAIN_5ADC Analog Input Bit 5
36VDD_MEM+1.8V 36XM0DATA0Memory port 0 Data Bit 0
37VDD_MEM+1.8V 37XMMC2DATA3DATA [3] (SD/SDIO/MMC card interface channel 2)
38VDD_MEM+1.8V 38XMMC2CMDCOMMAND/RESPONSE (SD/SDIO/MMC card interface channel 2)
39VDD_MEM+1.8V 39XMMC2DATA1DATA [1] (SD/SDIO/MMC card interface channel 2)
40VDD_MEM+1.8V 40XMMC2CLKCLOCK (SD/SDIO/MMC card interface channel 2)
41XMMC3CDNCARD DETECT (SD/SDIO/MMC card interface channel 3) 41XM0DATA3Memory port 0 Data Bit 3
42L3MODESPI clock for channel 1 42XM0DATA12Memory port 0 Data Bit 12
43GPDB1_HDMI_I2C_ENSPI chip select (only for slave mode) for channel 0 43XM0DATA14Memory port 0 Data Bit 14
44GPA1_2_3G_ENSPI master input / slave output line for channel 1 44XM0DATA7Memory port 0 Data Bit 7
45GNDGND 45XjTRSTnXjTRSTn (TAP Controller Reset) resets the TAP controller at start.
If debugger (black ICE) is not used, XjTRSTn pin must be at L
or low active pulse. Pull-down resistor is connected.
46GNDGND 46XM0DATA4Memory port 0 Data Bit 4
47GNDGND 47XM0DATA5Memory port 0 Data Bit 5
48CAM_B2_D1Camera data bit 1 48GNDGND
49GNDGND 49XM0WENMemory Port 0 SROM / OneNAND Write Enable
50CAM_B2_D6Camera data bit 6 50GNDGND
(MSM_ADDR [13] should be '0')
52XM0OENMemory Port 0 SROM / OneNAND Output Enable
53CAM_B2_D2Camera data bit 2 53XM0CSN0Memory Port 0 SROM Chip select support up to 2 memory bank
54UART2_TXUART2 Transit data 54GNDGND
55UART2_RXUART2 Receive data 55XdacOUTAnalog output of DAC
56UART1_CTSUART1 Clear To Send 56XpwmTOUT3PWM Timer Output
57GNDGND 57GPJ0_0_MOTERCOMMAND/RESPONSE (SD/SDIO/MMC card interface channel 3)
58UART2_CTSUART2 Clear To Send 58XI2CSCL0IIC-bus data for channel 0
59UART2_RTSUART2 Request To Send 59L3CLOCKPWM Timer Output
60UART1_RTSUART1 Request To Send 60XMMC1DATA0DATA [0] (SD/SDIO/MMC card interface channel 1)
61UART1_TXUART1 Transit data 61XMMC1CDNCARD DETECT (SD/SDIO/MMC card interface channel 1)
62UART1_RXUART1 Receive data 62XMMC1DATA1DATA [1] (SD/SDIO/MMC card interface channel 1)
63XMMC0CLKCLOCK(SD/SDIO/MMC card interface channel 0) 63XMMC0DATA2DATA [2] (SD/SDIO/MMC card interface channel 0)
64XMMC0DATA1DATA [1] (SD/SDIO/MMC card interface channel 0) 64XMMC0CMDCOMMAND/RESPONSE (SD/SDIO/MMC card interface channel 0)
65GNDGND 65XMMC0CDNCARD DETECT (SD/SDIO/MMC card interface channel 0)
66GNDGND 66NPBINManual Reset
67XMMC1CLKCLOCK(SD/SDIO/MMC card interface channel 1) 67GNDGND
68XMMC1DATA2DATA [2] (SD/SDIO/MMC card interface channel 1) 68GNDGND
69SD2WP33SPI clock for channel 0 69GNDGND
70XpwmTOUT2PWM Timer Output 70VDD_ALL+5V
71XpwmTOUT1PWM Timer Output 71VDD_ALL+5V
72XMMC3CLKCLOCK(SD/SDIO/MMC card interface channel 3) 72VDD_ALL+5V
74GPG1_0_MOTERDATA [1] (SD/SDIO/MMC card interface channel 3) 74VDD_ALL+5V
75XMMC3DATA3DATA [3] (SD/SDIO/MMC card interface channel 3) 75VDD_ALL+5V
76XMMC3DATA0DATA [0] (SD/SDIO/MMC card interface channel 3) 76GNDGND
77GPA1_3_3G_RSTSPI master output / slave input line for channel 0 77GNDGND
78GPG1_7_3G_DISSPI chip select (only for slave mode) for channel 1 78GNDGND

CN3   CN4
Pin Signal Description Pin Signal Description
1VDD_RTC+5V 1VDD_1V8+1.8V
2VDD_RTC+5V 2VDD_1V8+1.8V
3DVI_IRQKeyIF_Column_data[4] 3XI2SSDO0_2IIS-bus serial data output for channel 0 (Lower Power Audio)
4XUODRVVBUSUSB OTG charge pump enable 4XHDMIREXTHDMI Phy Registance
8XadcAIN_3ADC Analog Input Bit 3 8XHDMITX0NTMDS output data pair
9XadcAIN_0ADC Analog Input Bit 0 9XHDMITX0PTMDS output data pair
10XOM4Boot strap pin 10GNDGND
11XOM5Boot strap pin 11XHDMITX2NTMDS output data pair
12XEINT1_NPBSTATExternal interrupt 12XHDMITX2PTMDS output data pair
13XEINT5_CHR_FULLExternal interrupt 13GNDGND
14XEINT3_VSELExternal interrupt 14XPCMEXTCLK0PCM External Clock for channel 0
15XEINT10_BACKKEYBack Key 15XEINT10_BACKKEYExternal interrupt
16XEINT7_MENUKEYMenu Key 16XEINT7_MENUKEYExternal interrupt
17XEINT12/HDMI_CECConsumer Electronics Control 17XMMC2DATA2SD card data 2
18XEINT14_GSENSOR_INTExternal interrupt 18XEINT14_GSENSOR_INTExternal interrupt
19HOTPLUG_DVI_IOnDVI-D hot Plug Detect 19XMMC2DATA0SD card data 0
20CAM2_RSTExternal interrupt 20CAM2_RSTExternal interrupt
21XEINT24_KEY_UNDExternal interrupt 21XI2SSDO0_1IIS-bus serial data output for channel 0 (Lower Power Audio)
22XEINT26_VOL-External interrupt 22XMMC2CDNCard Detect for SDMMC2
23XEINT13/HDMI_HPDHot plug-and-play detect 23PCM_SOUT1_BTIIS-bus serial data output for channel 1
24XEINT28External interrupt 24PCM_SIN1_BTIIS-bus serial data input for channel 1
25XCLKOUTClock out signal 25XVVD20LCD pixel data output for RGB interface
26XUHPWRENUSB HOST charge pump enable 26XVVD21LCD pixel data output for RGB interface
27XI2CSDA1IIC serial bidirectional data 27XVVD19LCD pixel data output for RGB interface
28XI2CSCL1IIC master serial clock 28XVVD22LCD pixel data output for RGB interface
29XI2CSCL2IIC master serial clock 29XVVD5LCD pixel data output for RGB interface
30XUODPUSB Data+ 30XVVD13LCD pixel data output for RGB interface
31XUODMUSB Data- 31XVVD3LCD pixel data output for RGB interface
32UART0_RXUART0 Receive data 32XVVD2LCD pixel data output for RGB interface
33GNDGND 33XVVD8LCD pixel data output for RGB interface
34CAM_B_D1Camera data bit 1 34XVVD1LCD pixel data output for RGB interface
35CAM_B_D0Camera data bit 0 35XVVD0LCD pixel data output for RGB interface
36CAM_B_HREFHorizontal Sync, driven by Camera processor A 36XVVDENData Enable for RGB interface
37CAM_B_VSYNCVertical Sync, driven by Camera processor A 37XVVCLKVideo Clock for RGB interface
38GSOKeyIF_Row_data[4] 38XadcAIN_2ADC Analog Input Bit 2
39XadcAIN_1ADC Analog Input Bit 1 39XadcAIN_8ADC Analog Input Bit 8
40GSIKeyIF_Row_data[3] 40XVHSYNCHorizontal Sync Signal for RGB interface
41CAM_B_D7Camera data bit 7 41XUHDPUSB HOST Data pin DATA(+)
42CAM_B_D6Camera data bit 6 42XUHDMUSB HOST Data pin DATA(-)
43XUOVBUS+5V 43XUOREXTUSB OTG External 44.2ohm (+/- 1%) resistor connection
44CAM_B_CLKOUTMaster Clock to the Camera processor A 44HUHREXTUSB HOST External 44.2ohm (+/- 1%) resistor connection
45CAM_B_D5Camera data bit 5 45XUOIDUSB OTG Mini-Receptacle Identifier
46CAM_B_FIELDSpecifies the Field signal driven by external Camera processor A 46XI2CSDA2I2C-BUS Interface2 Serial Data Line
47CAM_B_D3Camera data bit 3 47UART0_TXUART0 Transit data
48CAM_B_D2Camera data bit 2 48XadcAIN_9ADC Analog Input Bit 9
49CAM_B_D4Camera data bit 4 49XVVD7LCD pixel data output for RGB interface
50CAM_B_PCLKPixel Clock, driven by Camera processor A 50XVVD11LCD pixel data output for RGB interface
51XEINT0_NIRQExternal interrupt 51XVVD6LCD pixel data output for RGB interface
52XEINT4_LCD_ON/OFFNC 52XVVD16LCD pixel data output for RGB interface
53XEINT8_HOMEKEYHome Key 53XVVD10LCD pixel data output for RGB interface
54XEINT0_PWRHOLDExternal interrupt 54XVVD14LCD pixel data output for RGB interface
55NETINT33Receive Clock 55XVVD15LCD pixel data output for RGB interface
56XOM2Boot strap pin 56XVVD18LCD pixel data output for RGB interface
57XEINT9_CAP_TOUCH_RSTNC 57XVVSYNCVertical Sync Signal for RGB interface
58XNRESETSystem Reset 58XVVD9LCD pixel data output for RGB interface
59XnRSTOUTFor External device reset control 59XVVD4LCD pixel data output for RGB interface
60XOM1Boot strap pin 60XVVD12LCD pixel data output for RGB interface
61XOM0Boot strap pin 61XVVD23LCD pixel data output for RGB interface
62XnWRESETSystem Warm Reset 62XVVD17LCD pixel data output for RGB interface
63GNDGND 63XI2SLRCK0IIS-bus channel select clock for channel 0 (Lower Power Audio)
64XEINT6_CHRINGExternal interrupt 64XI2SSDO0_0IIS-bus serial data output for channel 0 (Lower Power Audio)
65CAM_RSTExternal interrupt 65XI2SSDI0IIS-bus serial data input for channel 0 (Lower Power Audio)
66GNDGND 66XI2SCDCLK0IIS CODEC system clock for channel 0 (Lower Power Audio)
67XEINT25_VOL+External interrupt 67XI2SSCLK0IIS-bus serial clock for channel 0 (Lower Power Audio)
68XEINT31_BACKKEYExternal interrupt 68PCM_SCLK1_BTIIS-bus serial clock for channel 1
69GNDGND 69PCM_FSYNC1_BTIIS CODEC system clock for channel 1
70XEINT15_VBUS_DET+3.2V 70XI2SSDO2_3GPCM Serial Data Output for channel 0
71XEINT17_WLAN_ENExternal interrupt 71XI2SSDI2_3GPCM Serial Data Input for channel 0
72XEINT16_BT_ENExternal interrupt 72GNDGND
73XEINT18_WLAN_IRQExternal interrupt 73XHDMITX1PTMDS output data pair
74XOM3Boot strap pin 74XHDMITX1NTMDS output data pair
76XPWRRGTONPower Regulator enable 76XHDMITXCPTMDS output clock pair -
77XRTCCLKORTC Clock out 77XHDMITXCNTMDS output clock pair +
78XEINT4_HUB_RSTKeyIF_Column_data[7] 78GNDGND
79XUHOVERCURUSB HOST overcurrent flag 79XM0DATA15Memory port 0 Data Bit 15
80XEINT27External interrupt 80XM0DATA6Memory port 0 Data Bit 6

Block diagram

  • Download Mechanical Dimensions Sheet
  • Ships from: China
    Lead time: 1 week

    This product was added to our catalog on Monday 16 January, 2012.


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