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AM1808 Sitara ARM9 CPU Module, Dual 3x27-pin 2.0mm-pitch Headers US$99.00

T400321
AM1808 Sitara ARM9 CPU Module, Dual 3x27-pin 2.0mm-pitch Headers

  • 375 MHz TI AM1808 ARM926 Microprocessor
  • On-board 128 MByte Mobile DDR2, 128 MByte NAND Flash, 8 Mbit SPI Flash
  • Measuring only 58 4 5mm, this Mini8118 processor card is a small and low-cost controller board designed to be the core processing component for your next embedded design. It is based on TI's AM1808 Sitara ARM9 application processor which is powered by a 375 MHz ARM926EJ-S RISC MPU core. The board has 128 Mbytes mobile DDR2, 128 Mbytes NAND Flash and an 8 Mbit SPI Flash. It has two 2.0mm-spaced 327-pin connectors to bring out many hardware peripheral signals and GPIOs from the CPU.

    This processor card also can be purchased with a development board.

    AM1808 CPU Module Features

      Mechanical Parameters

    • Dimensions: 58 45 mm (six-layer PCB design)
    • Working temperature: -45 to +85 C
    • Humidity Range: 20% to 90%
    • Power Consumption: 125mA @ 12V
    • Texas Instruments AM1808 Sitara ARM9 microcontroller

    • 375 MHz ARM926EJ-S RISC MPU, also supports 456 MHz operation
    • ARM9 Memory Architecture
    • Enhanced Direct-Memory-Access Controller 3 (EDMA3)
    • 128 KByte On-chip Memory
    • 1.8V or 3.3V LVCMOS IOs (except for USB and DDR2 interfaces)
    • Two External Memory Interfaces
    • Three Configurable 16550-type UART Modules
    • LCD Controller
    • Two Serial Peripheral Interfaces (SPI) each with multiple chip-selects
    • Two MMC/SD Card Interfaces with Secure Data I/O (SDIO) Interfaces
    • External Memory

    • 128 MByte Mobile DDR2
    • 128 MByte NAND Flash
    • 8 Mbit SPI Flash
    • On-board Headers and Signals Routed to Pins

    • TFT LCD interface (supports 16-bpp parallel RGB interface LCD)
    • Two 8-bit camera interfaces
    • JTAG Debugger Interface
    • USB 1.1 OHCI (Host) With integrated PHY (USB1)
    • USB 2.0 OTG Port With integrated PHY (USB0, Supportd High-/Full-/Low-Speed)
    • Two SPI interfaces (SPI0 multiplexed with MII)
    • Two inter-integrated circuit (I2C) bus interfaces (I2C1 multiplexed with UART2)
    • Five UART interfaces
    • 10/100Mbps Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module
    • Multichannel buffered serial ports (McBSP) with FIFO buffers
    • Four 64-bit general-purpose timers, each configurable (one configurable as watchdog)
    • Two 4-line SD/MMC card interfaces
    • GPIO (up to 9 banks of 16 pins of general-purpose input/output with programmable interrupt/event generation modes, multiplexed with other peripherals)

    AM1808 CPU Module Pinout

    CON1 (left side) CON2 (right side)
    Pin Signal Description Pin Signal Description
    1LCD_D0VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8] 1CAM_PCLK_A0VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] / UPP_2xTXCLK
    2LCD_D1VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9] 2CAM_D0VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV / PRU1_R31[29]
    3LCD_D2VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10] 3CAM_D1VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK / PRU0_R31[23]
    4LCD_D3VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11] 4CAM_D2VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER / PRU0_R31[24]
    5LCD_D4VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12] 5CAM_D3VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] / PRU0_R31[25]
    6LCD_D5VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13] 6CAM_D4VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] / PRU0_R31[26]
    7LCD_D6VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14] 7CAM_D5VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN / PRU0_R31[27]
    8LCD_D7VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15] 8CAM_D6VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] / PRU0_R31[28]
    9LCD_D8VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0] 9CAM_D7VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] / PRU0_R31[29]
    10LCD_D9VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1] 10CAM_FIELDVP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] / PRU0_R31[13]
    11LCD_D10VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2] 11CAM_HSYNCVP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] / PRU0_R31[14]
    12LCD_D11VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3] 12CAM_VSYNCVP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] / PRU0_R31[15]
    13LCD_D12VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4] 13uP_CAM_STRPRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT / GP6[8] / PRU1_R31[17]
    14LCD_D13VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5] 14CAM_XCLKB_A0PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]
    15LCD_D14VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6] 15CAM_D12VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] / PRU0_R31[12]
    16LCD_D15VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7] 16CAM_D11VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] / PRU0_R31[11]
    17DGNDPower ground 17CAM_D10VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] / PRU0_R31[10]
    18DGNDPower ground 18CAM_D9VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9]
    19DGNDPower ground 19CAM_D8VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
    20DGNDPower ground 20CAM_PCLK_A1VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16]
    21SATA_100M_CLKNSATA_REFCLKN 21DGNDPower ground
    22DGNDPower ground 22uP_RESETOUTnRESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]
    23DGNDPower ground 23uP_TDITDI
    24SATA_100M_CLKPSATA_REFCLKP 24uP_TDOTDO
    25UART4_TXAXR10 / DR1 / GP0[2] 25uP_TMSTMS
    26DGNDPower ground 26uP_TCKTCK
    27uP_SATA_RXPSATA_RXP 27uP_TRSTnTRST
    28UART4_RXAXR9 / DX1 / GP0[1] 28uP_EMU1uP_EMU1
    29DGNDPower ground 29uP_EMU0uP_EMU0
    30uP_SATA_RXNSATA_RXN 30uP_RTCKRTCK
    31UART5_TXAXR14 / CLKR1 / GP0[6] 31uP_USB1_DPUSB1_DP
    32DGNDPower ground 32uP_USB0_IDUSB0_ID
    33uP_SATA_TXNSATA_TXN 33DGNDPower ground
    34UART5_RXAXR13 / CLKX1 / GP0[5] 34uP_USB1_DMUSB1_DM
    35DGNDPower ground 35DGNDPower ground
    36uP_SATA_TXPSATA_TXP 36DGNDPower ground
    37MMC_WPEMA_A[7] / PRU1_R30[15] / GP5[7] 37uP_USB0_DPUSB0_DP
    38MMC_SD1_D0PRU0_R30[25]/MMCSD1_DAT[0]/UPP_CHB_CLOCK/GP8[15]/PRU1_R31[27] 38DGNDPower ground
    39MMC_SD1_CLKPRU0_R30[24]/MMCSD1_CLK/UPP_CHB_START/GP8[14]/PRU1_R31[26] 39DGNDPower ground
    40LCD_AC_ENB_CSNLCD_AC_ENB_CS/GP6[0]/PRU1_R31[28] 40uP_USB0_DMUSB0_DM
    41MMC_SD1_CMDPRU0_R30[23]/MMCSD1_CMD/UPP_CHB_ENABLE/GP8[13]/PRU1_R31[25] 41TP_SPI1_SCSn1SPI1_SCS[1] / EPWM1A / PRU0_R30[7] / GP2[15] / TM64P2_IN12
    42MMC_SD1_D2VP_CLKOUT2/MMCSD1_DAT[2]/PRU1_R30[2]/GP6[3]/PRU1_R31[3] 42uP_SPI1_SOMISPI1_SOMI / GP2[11]
    43LVDS_ENAMUTE/PRU0_R30[16]/UART2_RTS/GP0[9]/PRU0_R31[16] 43uP_SPI1_SIMOSPI1_SIMO / GP2[10]
    44MMC_SD1_D1VP_CLKIN3/MMCSD1_DAT[1]/PRU1_R30[1]/GP6[2]/PRU1_R31[2] 44uP_SPI1_ENANSPI1_ENA / GP2[12]
    45MMC_SD1_D3VP_CLKIN2/MMCSD1_DAT[3]/PRU1_R30[3]/GP6[4]/PRU1_R31[4] 45TP_BUSYEMA_A[5] / GP5[5]
    46+3P3V_DEV_ENPRU0_R30[30]/UHPI_HINT/PRU1_R30[11]/GP6[12] 46uP_SPI1_CLKSPI1_CLK / GP2[13]
    47LCD_ENPRU0_R30[29]/UHPI_HCNTL0/UPP_CHA_CLOCK/GP6[11] 47uP_NMInRSVDN
    48UART3_RXEMA_A[7]/PRU1_R30[15]/GP5[7] 48DGNDPower ground
    49LCD_VSYNCMMCSD1_DAT[4]/LCD_VSYNC/PRU1_R30[4]/GP8[8]/PRU1_R31[5] 49DGNDPower ground
    50LCD_HSYNCMMCSD1_DAT[5]/LCD_HSYNC/PRU1_R30[5]/GP8[9]/PRU1_R31[6] 50I2C0_SCLSPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]
    51LCD_PCLKMMCSD1_DAT[7]/LCD_PCLK/PRU1_R30[7]/GP8[11] 51I2C0_SDASPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]
    52MII_TXD1AXR1 / DX0 / GP1[9] / MII_TXD[1] 52UART2_RXDSPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3]
    53MII_TXD2AXR2 / DR0 / GP1[10] / MII_TXD[2] 53MMC_CDEMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1] B
    54MII_TXD3AXR3 / FSX0 / GP1[11] / MII_TXD[3] 54DGNDPower ground
    55MII_COLAXR4 / FSR0 / GP1[12] / MII_COL 55UART2_TXDSPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2]
    56MII_TXD0AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0 56SD0_DATA1EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4] / PRU1_R31[20]
    57MII_TXENAXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6] 57SD0_DATA0EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5] / PRU1_R31[21]
    58DGNDPower ground 58UART1_TXDSPI1_SCS[2] / UART1_TXD / SATA_CP_POD / GP1[0]
    59MII_TXCLKAXR5 / CLKX0 / GP1[13] / MII_TXCLK 59SD0_CLKMMCSD0_CLK / PRU1_R30[31] / GP4[7] / PRU1_R31[23]
    60AIC_WCLKAFSX / GP0[12] / PRU0_R31[19] 60SD0_CMDEMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6] / PRU1_R31[22]
    61UART3_TXAXR12 / FSR1 / GP0[4] 61UART1_RXDSPI1_SCS[3] / UART1_RXD / SATA_LED / GP1[1]
    62AIC_BCLKACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21] 62SD0_DATA3EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2] / PRU1_R31[18]
    63+3P3VPower 3.3V 63SD0_DATA2EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3] / PRU1_R31[19]
    64AIC_MCLK/UART1_CTSNAHCLKX/USB_REFCLKIN/UART1_CTS/GP0[10]/PRU0_R31[17] 64WLAN_WAKEEMA_CS[2] / GP3[15]
    65MII_MDCSPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDIO_CLK / TM64P0_IN12 65WLAN_RESETEMA_A[6] / GP5[6]
    66DEEPSLEEPRTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP 66WLAN_HOST_WAKEEMA_CS[0] / GP2[0]
    67USER_MENUEMA_A[10] / PRU1_R30[18] / GP5[10] 67BT_HOST_WAKEEMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]
    68MII_RXERSPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER 68BT_WAKEEMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13]
    69MII_RXD0SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] / SATA_CP_DET 69BT_RSTEMA_CS[5] / GP3[12]
    70USER_MENUEMA_A[10] / PRU1_R30[18] / GP5[10] 70BUZZERAXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]
    71MII_RXDVSPI0_ENA / EPWM0B / PRU0_R30[6] / MII_RXDV 71LCD_PWMAXR7/EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]
    72MII_MDIOSPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO_D / TM64P1_IN12 72VCC_RTC1.2V RTC Power
    73XEINT16EMA_A[4] / GP5[4] 73+3P3V_STBPower 3.3V
    74MII_RXD3SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3] 74USB_RTSTnEMA_A[8] / PRU1_R30[16] / GP5[8]
    75MII_CRSSPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS 75uP_RESETn_KEYCPU reset input
    76DGNDPower ground 76+3P3V_STBPower 3.3V
    77MII_RXCLKSPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK 77DGNDPower ground
    78MII_RXD2SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2] 78USB0_VBUSUSB0_VBUS
    79PG_400MSCPU reset input 79UART2_RTSAMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]
    80VCORE_EN+1P2V_CORE_EN 80UART1_RTSnAHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18]
    81MII_RXD1SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] / SATA_MP_SWITCH 81WL_BT_REG_ONEMA_CS[4] / GP3[13]

    AM1808 CPU Module Resources

    Ships from: China
    Lead time: 1 week


    This product was added to our catalog on Monday 29 October, 2012.

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